Floorplanning takes in some of the geometrical constraints in a layout. Examples of this are:
bonding pads for off-chip connections (frequently the use of wire bonding) are generally located at the circumference of the chip;
line drivers regularly should be located as close to bonding pads as possible;
chip location is therefore in a few cases given a minimal area as a way to suit within the required variety of pads;
areas are clustered that allows you to restrict records paths hence regularly presenting defined structures along with cache RAM, multiplier, barrel shifter, line driver and arithmetic common sense unit;
bought intellectual assets blocks (IP-blocks), which includes a processor core, are available predefined place blocks;
a few IP-blocks come with legal obstacles along with allowing no routing of indicators directly above the block.
Mathematical fashions and optimization problems
In some approaches the floorplan may be a partition of the entire chip place into axis aligned rectangles to be occupied by IC blocks. This partition is concern to diverse constraints and requirements of optimization: block vicinity, factor ratios, estimated overall measure of interconnects, and so forth.
locating top floorplans has been a research area in combinatorial optimization. maximum of the troubles associated with locating premiere floorplans are NP-difficult, i.e., require great computational sources. consequently, the most common approach is to apply various optimization heuristics for locating precise solutions.
every other approach is to limit layout technique to positive training of floorplans, which include sliceable floorplans.
A sliceable floorplan, with a slicing order indicated
The handiest non-sliceable floorplan
A sliceable floorplan is a floorplan that can be defined recursively as described below. 
A floorplan that consists of a single square block is sliceable.
If a block from a sliceable floorplan is cut (“sliced”) in two through a vertical or horizontal line, the resulting floorplan is sliceable.
Sliceable floorplans had been used in a number of early digital design Automation gear for some of motives. Sliceable floorplans can be easily represented by means of binary bushes (extra specifically, ok-d trees), which correspond to the order of reducing. greater importantly, some of NP-tough problems with floorplans have polynomial time algorithms when constrained to sliceable floorplans.